Hello Rob, Just a quick update after my last reply. I managed to get the DAC to output signal today however the DAC configuration I changed to get it working confused me. The change I did was in Config73 (0x49). I had to assign ALL lanes to Link 0 even though the design only uses 2 lanes (Lane 0 and Lane 1). Is there any documentation (e.g. errata, application notes etc) that explains why this would be so? After getting the DAC to output, now the issue I am troubleshooting is that the f r equency of the DAC output is 10x slower than the data I loaded (e.g. a 50 MHz waveform is output as 5 MHz). I have verified that the data generated and loaded to the DAC is as expected (i.e. If a 50 MHz waveform is desired, data generated is for 50 MHz and data transmitted to the DAC is 50 MHz). Any idea what would be the cause? Again thank you for your help in advance. Regards, Tai
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