Hello Liston, The FPGA device clock architecture will depend on the basis of the JESD204 IP. This is a very specific requirement for Altera IP, and unfortunately, I do not have much insight on this. For example, TI's JESD204C IP may also be different from Altera's JESD204B IP. You can take a look through the IP request page below: https://www.ti.com/tool/TI-JESD204-IP
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