Hi Konan, If saturation is detected, you can change the parameters and wait for some time before capturing the data again. You don't need to reset the device. You can also discard few samples. Output code of 0 during the saturation is not expected. You can refer to table 4 of the datasheet for saturation codes in 24 bit format. One safe way to detect saturation is to monitor the output and if it exceeds 0.95V, treat it as saturation. Regards, Prabin.
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Forum Post: RE: AFE4404: saturation of TIA output
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Forum Post: ADS131A02: Status registers indicating some errors
Part Number: ADS131A02 Hii, I’m using ADS131A02 in my design, it’s hooked up to a Raspberry pi 0 and i’m having some troubles while getting the data. Some details about my implementation, M0-High, M1 and M2 are Low. Hence configured to 24bit word, Asynchronous interrupt mode. AIN1N and AIN2N are connected to AGND Avdd is connected 3.3 V from Rpi. VNCP is tied to AGND. XTAL2 is tied to 16.384 Mhz crystal oscillator Fixed word size disabled, no CRC(checked in 0x0c register). Internal reference of 2.44 is enabled. I am able to get correct response for all the commands, However, the RREG(STAT_1) keeps giving me two errors for every sample: F_ADC and F_SPI bits are set. Following the datasheet, I read the STAT_P and STAT_N registers to see which channels are exceeding the threshold and I get a 0x0 3 in return for both of them, meaning that all channels are exceeding the positive and negative inputs. Regarding the SPI, when I read the STAT_S register, it is telling me that I have an error with F_FRAME ie., Not enough SCLKs are sent per frame. Can you help me to get rid of these errors??
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Forum Post: RE: ADS5401: Binary to Decimal conversion for temperature sensor register
Hi Team, Can I have any comments on this? Regards, Takashi Onawa
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Forum Post: RE: ADC128D818: When will address pins A0 & A1 (Pins 7 & 8) be interpreted?
Ok, precisely spoken, Tom wasn't wrong, but his statement led me make the wrong conclusion that power up is the only time the address pins are latched. If this would happened to be right, the set-up from data sheet's Fig. 38 shouldn't work out of the box.
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Forum Post: ADS4246: example binary file
Part Number: ADS4246 thanks for your answers so far :- We are going to capture 2 channels from the ADS4246EVM with the TSW1400 and save the data in binary format (since it will be 1Gbyte). I presume that the samples in the binary file alternate, ch0, ch1, ch0, ch1 etc. Is this correct? Do you have a small example 2-channel binary file that I could use for my testing? (I am still waiting to get the eval boards so I cannot create one myself.)
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Forum Post: RE: ADS1204: Influence of the Input Source Impedance
Hi Tom, I measure the output voltage of an inverter for a sensorless motor drive application. I have attached a sketch of the input stage, whereas Ain+ is the positive input pin of the ADS1204 . It's a single ended measurement and the negative input pin of the ADS1204 (Ain-) is connected to 2.5V. The source signal (Vin) is a sinusoidal signal (fundamental frequency 2kHz, amplitude 90V) which is pulse width modulated (switching frequency 40kHz). The last of the two 1nF is located close to the ADS1204 and is used to buffer the signal. I'd like to know what influence the high source impedance has on the gain, linearity and THD and how the improve the performance by altering the below circuit. Thank you and best regards Nicole
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Forum Post: ADS7953: Capacitance at REFP and REFM pins
Part Number: ADS7953 We are using the IC in the VQFN package. Which capacitance is the minimum required at the REFP/REFM pins? According latest datasheet it shall be 10uF. However in the issue C of the datasheet (SLAS605) in Figure 70 there is a layout example with 1uF capacitance value. So, at least the drawing is not in-line with the text within datasheet. If I can safely change the capacitor value from 10uF to 1uF this would help much to accommodate with the layout guide line and to save PCB space (smaller package size). Thanks in advance! Regards Andreas
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Forum Post: RE: AFE7070EVM: tsw1400
(Please visit the site to view this file)Hi Neeraj, we were trying to test AFE7071 with TSW1400, this we were doing as given in the user guide (page 7-8). we are uploading the report that we have made while trying to test the board. one thing that we observed is only LO signal we are getting at the output (RF OUT). another thing is the LED corresponding to LOCK is not glowing, which indicate PLL is not locked. we tried to upload the file that you sent, but then also results were same. Thanks and Regards Chandan Choudhary
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Forum Post: RE: ADS4245-EP: ADS4245-EP clkout is not proper
HI, as you wrote in last post, I check the power sequence for clock and the ADC. The ADC power 1.8V is almost 7 ms earlier compared to clock to be present for ADC. Pls check the Plot below. As you said I will confirm the probe impedance for both. I will upload the Plots with 100E termination on clk. Regarding boards, Even the third board which was working, now have same status. The details are : Board 1 and Board 2 - ADC output clk - CLKOUTp is present "100MHz", CLKOUTn - "Not present" Even then some how (may be as I am using differential LVDS receiver buffer inside FPGA), I am getting clk inside FPGA. because of which a function test is passing at present. But Note that still CLKOUTn is not present on Board 1 and Board 2. Board 3: Both ADC CLK p & n are continuously changing. they are not stable at 100 MHz. Kindly comment.
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Forum Post: RE: DAC8551: Serial interface specification of DAC8551 and DAC8560
Hello, Condition 2 can be avoided easily because the timing B in the figure is very clear. It is 13nsec before SCLK falling edge. But regarding condition 3, there is no way to know it. Because there is no definition about where is A. We absolutely need the information of where is A in the figure, meaning MAX value or something. Regards, Oba
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Forum Post: ADC12DJ2700: Recommended method of interfacing a LVDS source for the TMSTP inputs
Part Number: ADC12DJ2700 hello, I have a LVDS output from a Xilinx Ultrascale and would like to connect it to the TMSTP inputs, and use it as JESD204B SYNC. I understand that when TMSTP is used as JESD204B SYNC, it requires an active low signaling, thus DC coupling is required. Can you recommend on a way to do so? Xilinx LVDS spec: Thank you Gil
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Forum Post: RE: LMP90098: Variations in RTD data
Hey Joseph, I have already tried the mentioned hardware changes on board. Attached log files for your reference.(Please visit the site to view this file)(Please visit the site to view this file)
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Forum Post: ADS1256: Setting up the SPI Logic Analyzer for ADS1256
Part Number: ADS1256 Hi Chris, Sorry for asking too much. I wonder if you could help me with some of the basic logic analyzer setup for the SPI communication debugging on ADS1256 ? SCLK - pin 13 (SCK) DIN - pin 11 (MOSI) DOUT - pin 12 (MISO) DRDY - pin 9 CS - pin 10 (CS) RESET - pin 8 (or tie HIGH?) For the following pins, which should be set LOW, RISE, HIGH, FALL, or EDGE for the trigger type? Thanks, Khoi Ly
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Forum Post: WEBENCH® Tools/ADS7945EVM-PDK: ADS7945
Part Number: ADS7945EVM-PDK Tool/software: WEBENCH® Design Tools Hello, I'm using ADCPro v 2.0.1 build 4 and EVM ADS794xEVM v2.0.0.0 with ADS794xEVM-PDK. I have installed both applications and connected the boards according to the instruction. I get error message 6004 (as shown below attached). Please advise how I can resolve this? Thanks, -albin
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Forum Post: ADS4128: ADS4128 driving and analog filtering
Part Number: ADS4128 Hi, We need to digitize a signal using an ADS4128 @ 200MSPS for a battery powered instrument. The source impedance will be 50Ohms single ended. We need to filter this signal with the following specs: 50kHz to 50MHz -3dB bandwith. In order to limit the aliasing, we plan to use an analog LPF with an attenuation of -60dB @ 150MHz followed by a digital filter cutting all frequencies above 50MHz, in order to relax the analog LPF requirements. However, I don't know what's the best practice for the analog filtering in order to preserve the good performances of this ADC: Can we aggressively low pass filter between the ADC driver (we plan to use the FDA THS4541 ) and the ADC using an RLC topology, or should we keep a high bandwidth between the two in order to limit the ADC sampling glitches? For a 12 bit ADC, do you recommend filtering (before the ADC driver) using a single ended or a differential topology? Many thanks, Victor
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Forum Post: RE: CCS/ADS8699: ADS8699 SPI DMA example c code
Hello Dale, that's great. For a start, I could set the DATAOUT_CTL_REG value same as Table 6. in datasheets with: #define WRITE 0xD000 #define DATAOUT_CTL_REG 0x10 ADC_Command = WRITE + DATAOUT_CTL_REG; SPI1_ADC_TxBuffer[0] = (uint8_t)(ADC_Command >> 8); SPI1_ADC_TxBuffer[1] = (uint8_t)ADC_Command; SPI1_ADC_TxBuffer[2] = 0x55; SPI1_ADC_TxBuffer[3] = 0x08; SPI_transmitData(EUSCI_B0_BASE, SPI1_ADC_TxBuffer[0]); SPI_transmitData(EUSCI_B0_BASE, SPI1_ADC_TxBuffer[1]); SPI_transmitData(EUSCI_B0_BASE, SPI1_ADC_TxBuffer[2]); SPI_transmitData(EUSCI_B0_BASE, SPI1_ADC_TxBuffer[3]); __delay_cycles(4800000); And it looks good. But: 1. the 18bit value that I read out doesn't match with the range (0011=1.25*vref): Some printf from my 32bit read out (second number is the current 18bit adc value): Mean=158096 158096 10011010011001000000000000001100 Mean=158100 158105 10011010011001100100000000001100 Mean=158100 158100 10011010011001010000000000000000 Mean=158101 158103 10011010011001011100000000000000 Mean=158101 158102 10011010011001011000000000001100 Mean=158104 158108 10011010011001110000000000001100 Mean=158106 158109 10011010011001110100000000000000 Mean=158106 158106 10011010011001101000000000001100 Mean=158108 158110 10011010011001111000000000000000 Mean=158106 158105 10011010011001100100000000001100 Mean=158104 158102 10011010011001011000000000001100 Mean=158104 158104 10011010011001100000000000000000 Mean=158104 158104 10011010011001100000000000000000 Mean=158102 158101 10011010011001010100000000001100 Mean=158106 158111 10011010011001111100000000001100 Mean=158108 158111 10011010011001111100000000001100 Mean=158105 158103 10011010011001011100000000000000 Mean=158105 158105 10011010011001100100000000001100 Mean=158104 158104 10011010011001100000000000000000 Mean=158104 158105 10011010011001100100000000001100 Mean=158103 158103 10011010011001011100000000000000 Mean=158105 158108 10011010011001110000000000001100 Mean=158106 158108 10011010011001110000000000001100 Mean=158103 158101 10011010011001010100000000001100 Mean=158103 158103 10011010011001011100000000000000 Mean=158104 158106 10011010011001101000000000001100 Mean=158103 158102 10011010011001011000000000001100 Mean=158105 158107 10011010011001101100000000000000 Mean=158105 158105 10011010011001100100000000001100 Mean=158106 158107 10011010011001101100000000000000 Mean=158107 158108 10011010011001110000000000001100 Mean=158100 158094 10011010011000111000000000001100 My measurements and calculation: AVDD 5,063 V Ain 2,555 V ADC value 158105 digit ADC value 60,3 % of range Voltage_calc 4,236 V But with the setup 1.25*vref=5.12V I should have Voltage_calc=3.088V at 185105 digits !? 2. sometimes I read range = 0000b ?
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Forum Post: ADS4246: getting started with EVM
Part Number: ADS4246 My eval boards ADS4246EVM with the TSW1400 have arrived and I am trying to get the system up and running but need some help. The instructions are to start the software, select the 422x ADC and when prompted to upload the firmware click yes. After downloading the firmware, a message appears I can press OK and try to do a capture but get nothing displayed on the graph. I’ve tried a few times without success so need some help please. Could you also confirm the required clock characteristics for the ADC board? I cannot find any spec in the EVM documentation. I only need to work at 76MHz. Currently I am inputting 500mVp-k square wave at 76M.
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Forum Post: ADC12020: trigger for Data conversion
Part Number: ADC12020 Hi, team. I would like to know the method to set the trigger for data conversion in ADC12020 . Could you please let me know how to start sample & hold with arbitrary timing? Regards, Nagata.
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Forum Post: RE: DAC38J84: DAC38J84EVM + TSW14J10EVM + ZC706 issue
Ravikant, The 16-bit DAC resolution is the resolution of the DAC output swing and the granularity of the output swing (i.e. how fine we can represent the Y axis). It has nothing to do with the length of the pattern (i.e. X axis or time resolution). The length of the pattern is limited by your FPGA design. You will need to include DDR memory in your FPGA design to increase the length of the pattern being loaded onto the pattern generator. Using the on-chip memory of the FPGA sounds like are not sufficient for your design. -Kang
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Forum Post: AFE4300EVM-PDK: 296-37485-ND
Part Number: AFE4300EVM-PDK Thanks! So I write in that forum about my questions.
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