Part Number: AFE4300 Hi! I wonder to have more info about MMB3 board. I bought a AFE4300EVM and I have trying to use only the MMB3 board to new purposes. I can't find any information about, like a schematic, datashet, in/out pins, etc. And also, I need the code of the M430F449 to control my AFE4300 board on the MMB3 board. Thank You
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Forum Post: AFE4300: 296-37485-ND
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Forum Post: AMC7812: seeking support for I2C communication in AMC7812
Part Number: AMC7812 Hi, I am using a texas based I2C controller AMC7812 for reading ADC values of adc channels in AMC7812 . The master controller is AT32UC3a1512 of atmel. I am able to send the I2C commands from master but I am not getting any ack or any data from AMC7812 . Kindly suggest me how to get data from AMC7812 . I2C mode is enabled by grounding SPI/I2C pin and the slave ID is also selected based upon A0,A1 and A2 pins. Seeking urgent support on this issue.
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Forum Post: RE: ADS8509: ADC that can send its data as spi Master.
Dear Dale, unfortunately I don't have the option to write control registers (that was not necessary with the ADS8509 , which is currently used). Is there a way to get these ADCs into spi-master mode without writing control registers? Thank you Marco
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Forum Post: RE: TSW1400EVM: HSDC Pro v5 shows "No firmware. Please select a device to load firmware into the board." Also AFE5808EVM board in use.
Hi Michael, I most often see this issue when the power supply is not sourcing enough current. Please ensure the 5V supply is sourcing at least 3A of current. If the problem persists, the TSW1400 should be replaced, especially since this board had worked in the past. Best Regards, Dan
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Forum Post: TLC2543: Leakage current
Part Number: TLC2543 Hello, the leakage current of the TLC2543 is announced in the datasheet between -10µA and +10µA. Do you know if this dispersion between components is a random drift which follow a gaussian law ? If yes do you know the standard deviation of this variation ? Best regards, Nicolas Divel
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Forum Post: ADS114S06: PSRR vs. Frequency
Part Number: ADS114S06 Please provide a PSRR vs. frequency plot for ADS114S06 like we have for ADS1120 (figure 14 in the datasheet). Thanks!
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Forum Post: RE: ADS4128: ADS4128 driving and analog filtering
Hi Victor, Here are the front ends (transformer and Differential Amp) used on the ADS4128EVM (Evaluation Module). The diff amp input has pads available for some filtering if you would like to test your filter design. You should be ok to filter as described, but I would ensure that the 10 ohm resistors are present at the input of the ADC (located on the transformer input side) to reduce sampling glitch. Best Regards, Dan
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Forum Post: RE: ADS4246: getting started with EVM
Hi Ajayt, Is there an error or prompt that occurs in HSDC Pro when you try to capture? If not, do you see a noise floor in the FFT? Best Regards, Dan
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Forum Post: RE: Linux/ADS1299: I want more than data, Like ADS1299 eeg program
Hi Keunsoo, I apologize, I did not understand the question initially. What I think you're asking about is how to receive data continuously as opposed to one sample at a time. Correct? You want to do this without using the MMB0 motheboard, and use a Raspberrypi instead. Correct? Please review section 9.5 of the ADS1299 datasheet. Especially 9.5.3.7, RDATAC: Read Data Continuous. These threads should help as well: e2e.ti.com/.../2190119 e2e.ti.com/.../346609 e2e.ti.com/.../452144
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Forum Post: DAC161S997: RF Oscillating DAC
Part Number: DAC161S997 We have designed your DAC161S997RGH into a new line of 2-wire transmitters, and are having difficulty passing RF Immunity tests. Specifically, your DAC oscillates rail-to-rail at an RF frequency sweep between 400MHz and 500MHz. We are testing it at 10V/m, and it does pass at 3V/m field strength. Can you suggest how we can stabilize this DAC for better RF immunity above 3V/m?. I tried your paste from word function, but cannot get it to paste the circuit snippet of the DAC oscillator here. Please email me and I will send you the circuit. Thanks.
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Forum Post: ADC128S102: ADC128S102
Part Number: ADC128S102 I am seeing something other than all zeros in first 4 bits of the "Data Out" serial data after the CS for the ADC128S102 is asserted. Please see attached file which shows the timing from the data sheet. I highlighted in yellow where the 4 bits should be zero. The rest of the Data Out stream looks ok, i.e., the 12 bit ADC reading appears to be consistent with the voltage I presenting to the ADC. I can provide more details, but I'm just hoping that someone has seen this before and recognizes the problem.
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Forum Post: RE: ADS1256: Setting up the SPI Logic Analyzer for ADS1256
I have not tried the scope yet, but based on what you said, I would assume that the scope can handle the sharp corners for digital square waves? In other words, does the scope have enough bandwidth to capture the SPI signal? By wrapping the ground wire, I think you mean for each digital signal, I will provide a twisted pair with ground wire? I will look into the input voltage as well. Maybe what you say about the signal integrity is true, but I wonder why this problem only happens to DOUT (MISO) but not DIN (MOSI)? All of the SPI pins are connected from Arduino to breadboard, then from breadboard they are splitted to the logic analyzer and the ADS1256 . Thanks, Khoi Ly
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Forum Post: RE: ADS8920B: Replacing a Microchip MCP3550 ADC with an ADS8920B
Hi Ian, Take a look at section 7.5.3 in the datasheet which describes two data transfer time zones (Zone 1 and Zone 2). Zone 1 is the standard SPI transfer zone; Zone 2 is referred to as part of Enhanced SPI. MultiSPI refers to multiple SDO lines, but can also be thought as part of 'enhanced SPI' as well. Basically, Zone 2 allows a larger percentage of the cycle time to be used to read data out of the device, which lowers the SPI SCLK speed requirements. Reading in Zone 2 is controlled by the host timing (SCLK relative to the /CS, CONVST edge). MultiSPI requires writing to the configuration registers to enable multiple SDO lines (1x, 2x, 4x). There is a good White Paper that describes all of this in more detail. http://www.ti.com/lit/wp/sbay002/sbay002.pdf The table on the front page of the datasheet is approximate and assumes a single SDO line reading in Zone 2. Use the values in section 6.6, Timing Requirements, and equations 8 and 9 in section 7.5.3, to calculate the exact minimum SCLK frequency for different sampling rates. Example: Fsample=800kHz Tsample(Tcycle)=1250nS Tread-z2=1250nS-20nS-30nS=1200nS (equation 8) Fsclk=16/1200nS=13.33MHz for 16b data transfer (equation 9) Fsclk=18/1200nS=15MHz for 18b data transfer (16b data plus 2 parity bits) It never hurts to include a 10ohm series resistor in each digital line. This helps with high speed digital edges that could couple additional noise into the ADC. Depending on the FPGA used, you can usually slow the edge rates down. The ADS8920BEVM evaluation board has resistors, but just uses 0 ohm jumpers. I suggest using the EVM design and layout as a good starting point. http://www.ti.com/lit/ug/sbau270/sbau270.pdf Sharing the digital lines (except SDO) between multiple ADS8920B devices will not be an issue. The only limitation is that each device will be configured identically. Regards, Keith
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Forum Post: ADC12DJ3200EVM: Question on JMODE Documentation
Part Number: ADC12DJ3200EVM I am looking at some code that resembles JMODE0 Table 20. (page 66) of the ADC12DJ3200 documentation but I don't know where they get the bit ranges. This is what is looks like: s0 31:20 s8 19:8 s16 7:0 31:28 s24 27:16 s32 15:4 3:0 s2 63:52 s10 51:40 s18 39:32 63:60 s26 59:48 s34 47:36 35:32 s4 95:84 s12 83:72 s20 71:64 95:92 s28 91:80 s36 79:68 67:64 s6 127:116 s14 115:104 s22 103:96 127:124 s30 123:112 s38 111:100 99:96 s1 159:148 s9 147:136 s17 135:128 159:156 s25 155:144 s33 143:132 131:128 s3 191:180 s11 179:168 s19 167:160 191:188 s27 187:176 s35 175:164 163:160 s5 223:212 s13 211:200 s21 199:192 223:220 s29 219:208 s37 207:196 195:192 s7 255:244 s15 243:232 s23 231:224 255:252 s31 251:240 s39 239:228 227:224 Where do I find out the ranges? For example for s0 they have 31:20 where do they get this? Is this in the documentation? Also is there a place I can get this so I can reverse engineer this pattern for JMODE 11? Thanks, Zach
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Forum Post: RE: ADS7039-Q1: SPI timing, 16 SCK pulses input
Ryuji-san, Our recommendation is that you follow the guideline that you use 12 SCLKs to clock out the data and then return the /CS high. I don't know of any specific mode the device enters when you clock out 16 SCLKs. However, on the first clocking of after power-up, if there are 16 SCLKs the device enters offset calibration. Again, we just recommend sending the 12 SCLKs for reading the data. Joseph Wu
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Forum Post: RE: ADC12J4000: Frequency Measurement Error
Hi Florian If you are still encountering this issue can you provide any of the data files previously requested? If the issue is resolved please let me know.
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Forum Post: RE: ADS7950: MIN/MAX value for Gain Error in Range 2 case
The performance is similar to Range 1 performance but without values in the datasheet we are not able to provide minimum or maximum values for this specification. Regards, Cynthia
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Forum Post: RE: ADC12DJ2700: Recommended method of interfacing a LVDS source for the TMSTP inputs
Hi Gil The TMSTP+/- inputs use similar input circuitry to that of the CLK+/- and SYSREF+/- inputs. This was done to give better performance matching between those inputs and the signal applied to TMSTP. Unfortunately this means the DC-coupled TMSTP or /SYNC signal must meet the low common mode voltage requirements, which is not compatible with LVDS. There is no way to convert from the FPGA LVDS outputs to the TMSTP+/- inputs using discrete terminations. Using a resistor divider to achieve the needed common mode will result in the differential amplitude being lower than what is needed. The only solution is to use an LVDS to LCPECL or LVPECL buffer IC along with some additional board level termination resistors and set TMSTP_LVPECL_EN = 1. When using an FPGA LVDS output for JESD204B /SYNC a conversion IC is needed in either case. Therefore for simplicity we recommend using the /SYNC_SE input instead of the TMSTP+/- inputs. Best regards, Jim B
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Forum Post: RE: DAC3161: DAC3161 SPI communication problems
Thanks, DAN: Problem solved by ourselves. The solution from hardware engineer: VHDL language in one loop which is different from Verilog we are using. But the compiler didn’t give warning... Thanks. RM
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Forum Post: RE: ADS7953: Capacitance at REFP and REFM pins
Hello, the layout image was no updated, we made a note to make sure this is done. The capacitor size stated in the text is correct, 10uF, and applies to all the packages Regards, Cynthia
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