Hi Jim, thanks for your details. I've prepared two documents: - the first document is a descriprion of the board and the method used to sync the data; - the second document is the list of the command used to configure the ADC at the power on. I've problems to understand the way to attach these file. Can you help me? Thanks in advance. Best Regards. Daniele
↧
Forum Post: RE: TINA/Spice/ADC12DL3200: SYSREF processing activity
↧
Forum Post: RE: ADS1298: ADS1298 IC alternative
Sir, How i interface this ads1298 with Arduino uno using SPI Communication.
↧
↧
Forum Post: RE: ADS1298: ADS1298 IC alternative
Hello, Take a look at the FAQ below. This is all of the code support we provide for the ADS1298 at this time. e2e.ti.com/.../2866878
↧
Forum Post: RE: DAC37J82: JESD204B deterministic latency with Xilinx FPGA & DAC37J82 using AD9528
lhlhlhjay, See if the following document helps. Regards, Jim (Please visit the site to view this file)
↧
Forum Post: AFE4490SPO2EVM: AFE4490SPO2EVM
Part Number: AFE4490SPO2EVM Any news on Windows 10 64-bit signed drivers for this Texas Instruments board? Regards, David
↧
↧
Forum Post: RE: DAC37J82: JESD204B deterministic latency with Xilinx FPGA & DAC37J82 using AD9528
Jim thanks for your reply . Document SLAA696 give me some help but can't solve my problem.
↧
Forum Post: RE: AFE5818: HPF or DC compensation distortion?
Hi, We have not found any useful combination of LNA HPF disable/enable and PGA enable/disable or LNA_HPF_PROG or RED_LNA_HPF_3X. There is always significant distortion unless both LNA and PGA HPF are disabled (this is not a practical option). We have spent too much time trying different combinations. Please show us measurements and settings that doesn't cause distortion, e.g: * LNA HPF enable * PGA HPF enable * Vin = >200 Vpp at 10~100 kHz Thanks, Christer
↧
Forum Post: RE: ADS1298: Detection of Hardware Pace
Hi Ryan, It's Ahmed Sabry from Pulse for integrated solutions, Gain of the PGA is 6, the default one. The analog supply voltage are 5V with respect to the ground, no bi-polar voltages. The reference of the input signals is done internally using CONFIG resisters, which is 2.5V. We are trying to detect the Pacemaker small amplitudes (2mv with 2ms and 2mv with 0.1ms). Would you please specify more details about the test stated on your comment, and what do you mean by disconnection all circuitry?, currently i'm using the external circuit stated in the document issued by Tony Calabria, about the detection of Hardware Pace using Slope Detection, should i remove this circuit??
↧
Forum Post: DDC112: The problem of Download link of DDC11XEVM-PDK Plugin Installation
Part Number: DDC112 Hello， Our DDC11XEVM-PDK Plugin download link is down. Can someone please help to provide a good link please? Thanks http://www.ti.com/tool/ddc11xevm-pdk Best regards Kailyn
↧
↧
Forum Post: RE: ADS1298: Page 12, Figure 9 R1, R2, R3 User's Guide Clarification
Dear e2e, 9.3.1.6 it is not clear how R1 could have any influence since it is in series with infinite impedance looking into the non inverting on one side and an open circuit, a capacitor, for a dc.
↧
Forum Post: RE: DAC37J82: JESD204B deterministic latency with Xilinx FPGA & DAC37J82 using AD9528
lhlhlhjay, Send me the following information and I will send you a configuration file to try: LMFS values DAC Internal PLL or not. If using the PLL, what is the reference frequency? NCO or not. If you are using the NCO, at what frequency? DAC sample rate DAC data rate interpolation factor K value RBD value SYSREF frequency. Is this pulsed or continuously running? Regards, Jim
↧
Forum Post: RE: DAC37J82: JESD204B deterministic latency with Xilinx FPGA & DAC37J82 using AD9528
One more thing. Is SYSREF AC or DC coupled? If DC coupled, what is the common mode voltage level?
↧
Forum Post: RE: AFE5809: Should Analog and Digital GND be splitted in layout?
Hi Chen now we do place CLOCK IC ( LMK00301 ) and ADC_CLK in digital region. as I drawed in pitcure, you can see that ADC_CLK pins in AFE pin-out is on the right side of the red GND-splitting-line, not only ADC_CLK traces but also CW_CLK traces will run across the DGND-AGND areas. Does your sytem engineer actually implies that they usually use a WHOLE GND for AFE's AVSS and DVSS for AFE5809 in PCB practice ? It would be great if TI experts could kindly provide more insights and suggetions. Thanks very much! Yi
↧
↧
Forum Post: RE: ADS1256: ADS1256 for photovoltaic design using arduino platform
Hi Chris, I am implementing below on ESP32 there seems to be some spiking happening especially close to the lower level of signals, any suggestion to improve? I am also noticing that I cannot get the registers to configure properly, and cannot control PGA etc. (Please visit the site to view this file)
↧
Forum Post: RE: DDC112: The problem of Download link of DDC11XEVM-PDK Plugin Installation
Hello Kailyn, We are in the process of getting the approval to release the software to the web. Send in your request to ddcxxx-support@list.ti.com along with a reference to this e2e post and I will provide the software link to your email address.
↧
Forum Post: RE: AFE4490SPO2EVM: AFE4490SPO2EVM
Hi David, Unfortunately, at this time, we still don't have the 64-bit signed drivers for the AFE4490EVM. We are looking into this and do not have a specific date when the drivers will be available.
↧
Forum Post: ADS1298: ADS1298ECGFE
Part Number: ADS1298 Dear e2e, 9.3.1.6 it is not clear how R1 could have any influence since it is in series with infinite impedance looking into the non inverting on one side and an open circuit, a capacitor, for a dc.
↧
↧
Forum Post: ADS1298R: ADS1298 Test signals not generating, DRDY pin stops to generate low signal.
Part Number: ADS1298R I had asked this question on the forum previously and I had concluded from the discussion there that the problem is with my PCB design and I changed it to look exactly like the ADS1298 ECGFE_PDK board. I am still facing these issues: 1. DRDY Pin stops toggling after 10 or 20 times (the number of times it toggles before stopping is not constant but it is under 50). 2. If it doesn't stop toggling, then Data should come right?!.. well I keep receiving 0 (Which I conclude, as the ADS stops sending any data at all, that my controller interprets it as 0). 3. I read about internally generated test signals in ADS, and that receiving them validates that the signal path is clear. So I tried to test it (I think checking internal test signals is irrelevant to how or whether ECG leads are connected). IF that is correct, I should get 1Hz square waves. I don't get them. Problems 1 & 2 prevail. SPI communication works, Register Reads and Writes work, Tried and Tested. I am using STM32L04 as my MCU and DRDY pin is configured as Input with pull up resistors enabled. Voltage at VCAP1 pin is 1.1V. So that is checked and out of the way. I have spent a lot of time and resources trying to recreate the board but it still isn't working so I am out of wits. I have concluded that the Digital part of the ADS works fine, but the ADC part doesnt work at all. Is this conclusion correct given the symptoms? I have inserted the images of the front: And the back of the board: This is the schematic and layout files: (Please visit the site to view this file) Thanks for Help, Ninad Gandhi. (Please visit the site to view this file)
↧
Forum Post: RE: ADS1298R: ADS1298 Test signals not generating, DRDY pin stops to generate low signal.
Also here is an image of how the DRDY signal transitions after sending start pulse and after some toggling, it stops to toggle. (the number of pulses before it stops toggling is random, but few).
↧
Forum Post: RE: DAC37J82: how to config the parameters for DAC37J82
Thank you Regards, Shai
↧
